| ISBN: ISBN: 0-7695-0146-X
|
| ISBN: ISSN: 1093-0167
|
| ISBN: DOI: 10.1109/VTEST.1999.766693
|
| |
| description |
This paper presents a new technique for on-line consistency checking
of embedded DRAMs. The basic idea is to use the refresh cycle for
concurrently computing a test characteristic of the memory contents
and compare it to a precomputed reference characteristic.
Experiments show that the proposed technique significantly reduces
the time between the occurrence of an error and its detection (error
detection latency). It also achieves a very high error coverage at
low hardware costs. Therefore it perfectly complements standard
on-line checking approaches relying on error detecting codes, where
the detection of certain types of errors is guaranteed, but only
during READ operations accessing the erroneous data.
|
| publisher |
Institute of Electrical and Electronics Engineers
|
| type |
Text
|
| Article in Proceedings
|
| source |
In: Proceedings of the 17th IEEE VLSI Test Symposium (VTS), Dana
Point, CA, April 25-29, 1999, pp. 384-390
|
| contributor |
Rechnerarchitektur (IFI)
|
| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
|